JEDEC Solid State Technology Association Announces Publication of JESD79-5C DDR5 SDRAM Standard
JEDEC Solid State Technology Association, the leading organization in standards development for the microelectronics industry, has released the JESD79-5C DDR5 SDRAM standard. This update to the JEDEC DDR5 SDRAM standard includes enhancements to improve reliability, security, and performance across various applications, from high-performance servers to emerging technologies like AI and machine learning. The JESD79-5C standard is now available for download from the JEDEC website.
JESD79-5C introduces Per-Row Activation Counting (PRAC) to enhance DRAM data integrity. PRAC accurately counts DRAM activations on a wordline level, allowing the system to pause traffic and implement mitigative measures when excessive activations are detected. This feature ensures a more accurate and predictable approach to addressing data integrity challenges through close coordination between the DRAM and the system.
Additional features in JESD79-5C DDR5 include:
- Expansion of timing parameters definition from 6800 Mbps to 8800 Mbps
- Inclusion of DRAM core timings and Tx/Rx AC timings extended up to 8800 Mbps
- Introduction of Self-Refresh Exit Clock Sync for I/O Training Optimization
- Incorporation of DDP (Dual-Die Package) timings
- Deprecation of PASR (Partial Array Self Refresh) to address security concerns
Mian Quddus, JEDEC Board of Directors Chairman, expressed his excitement about the collaborative efforts of JEDEC's JC-42 Committee for Solid State Memory in advancing the DDR5 standard. He emphasized that the new features in JESD79-5C aim to meet the evolving industry demands for security, reliability, and performance.
Christopher Cox, JC-42 Committee Chair, highlighted the introduction of PRAC as a key component of the DDR5 update to ensure DRAM data integrity. The committee is working on incorporating this feature into other DRAM product families within JEDEC.
