TSMC Announces 3Dblox 2.0 Open Standard and 3DFabric Alliance Achievements

TSMC has unveiled the new 3Dblox 2.0 open standard and highlighted the accomplishments of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum. The 3Dblox 2.0 introduces early 3D IC design capabilities to enhance design efficiency, while the 3DFabric Alliance continues to drive integration in memory, substrate, testing, manufacturing, and packaging. TSMC is committed to advancing 3D IC innovation and making its comprehensive 3D silicon stacking and advanced packaging technologies more accessible to all customers.

"As the industry embraces 3D IC and system-level innovation, collaboration across the industry has become even more crucial than when we launched OIP 15 years ago," said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. "Through our ongoing collaboration with OIP ecosystem partners, we enable customers to leverage TSMC's leading process and 3DFabric technologies to achieve unprecedented performance and power efficiency in next-generation AI, HPC, and mobile applications."

"We have been closely working with TSMC on advanced 3D packaging technology, which allows AMD's next-generation MI300 accelerators to deliver industry-leading performance, memory footprint, and bandwidth for AI and supercomputing workloads," said Mark Fuselier, senior vice president of Technology and Product Engineering at AMD. "Together with their 3DFabric Alliance partners, TSMC has built a robust 3Dblox ecosystem that has helped AMD accelerate time-to-market for our 3D chiplet product portfolio."

3Dblox 2.0

Introduced last year, the 3Dblox open standard aims to modularize and streamline 3D IC design solutions for the semiconductor industry. With contributions from a vast ecosystem of companies, 3Dblox has emerged as a critical design enabler for future 3D IC advancements.

The newly launched 3Dblox 2.0 enables 3D architecture exploration with an innovative early design solution for power and thermal feasibility studies. Designers can now, for the first time in the industry, integrate power domain specifications and 3D physical constructs in a holistic environment and simulate power and thermal aspects for the entire 3D system. 3Dblox 2.0 also supports chiplet design reuse features, such as chiplet mirroring, to further enhance design productivity.

3Dblox 2.0 has gained support from key EDA partners to develop design solutions that fully align with TSMC's 3DFabric offerings. These comprehensive design solutions provide designers with valuable insights to make early design decisions, accelerating the design process from architecture to final implementation.

TSMC has also established the 3Dblox Committee, an independent standard group, with the aim of creating an industry-wide specification that enables system design with chiplets from any vendor. Working with key members including Ansys, Cadence, Siemens, and Synopsys, the committee consists of ten technical groups focusing on different subjects and proposes enhancements to the specifications while ensuring the interoperability of EDA tools. Designers can now download the latest 3Dblox specifications from the 3dblox.org website and find more information about 3Dblox and its tool implementation by EDA partners.

3DFabric Alliance Achievements

TSMC's 3DFabric Alliance, the first of its kind in the semiconductor industry, has experienced significant growth over the past year. The alliance aims to provide customers with a comprehensive range of proven solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. Currently, the alliance has 21 partners across the industry collaborating and innovating together.

Memory Collaboration: TSMC has collaborated closely with key memory partners, including Micron, Samsung Memory, and SK hynix, to meet the increasing demand for SRAM memory and higher DRAM memory bandwidth in generative AI and large language model-related applications. This collaboration has led to advancements in HBM3 and HBM3e, enabling the development of more memory capacity for generative AI systems.

Substrate Collaboration: TSMC has successfully worked with substrate partners IBIDEN and UMTC to define a Substrate Design Tech file that facilitates substrate auto-routing, resulting in significant efficiency and productivity gains. The company has initiated a three-way collaboration with substrate and EDA partners to achieve 10x productivity gains through automatic substrate routing. The collaboration also includes design for manufacturing (DFM) enhancement rules to reduce stress hotspots in substrate design.

Testing Collaboration: TSMC is collaborating with automatic test equipment (ATE) partners Advantest and Teradyne to address various 3D test challenges, aiming to minimize yield loss and improve power delivery efficiency for chiplet testing. To demonstrate high-speed test access for 3D stack testing through a functional interface, TSMC is working with Synopsys and ATE partners on a silicon demonstrator to achieve a 10x testing productivity boost. The company is also collaborating with all design-for-test (DFT) EDA partners to ensure effective and efficient interface testing.